Prototypes BootP34 · RISC-V computer

Boot against riscv-tests

riscv-tests is the official test suite of the RISC-V instruction set. Each test below is the suite’s own assembly, compiled with clang for RV32IMA. It runs on Boot’s processor in this page, one instruction at a time. A test passes when it writes 1 to its tohost address. When a check fails, it writes the number of that check instead.

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TestSuiteResultInstructionsFailed check

Disassembly

Press a test to see its code, with the instruction where it ended marked.

    How Boot is built
    1. Boot is a RISC-V computer written for this prototype in plain JavaScript, with no dependencies. Its processor runs RV32IMA: the base integer instructions, multiply and divide, and atomics. It has the CSR instructions, machine mode and user mode, interrupts and traps.
    2. The processor runs in a Web Worker, so the page stays responsive. It fetches each instruction from RAM, decodes it with shifts and masks, and executes it in one loop over typed arrays that allocates no memory per instruction. The worker sends the page what the UART printed and how far the computer has come.
    3. Around the processor is a small machine: 64 MiB of RAM, a 16550 serial port for the terminal, a timer, and a register that powers off and restarts. Boot writes a device tree that describes this machine to Linux, in the binary format Linux reads. Five instructions of firmware put its address in a register and jump to the kernel.
    4. The kernel is Linux 6.8 for 32-bit RISC-V without memory protection, with BusyBox for the shell and its programs. It is the same file anyone can download.
    5. Time on this computer is counted in instructions. The timer moves one tick for every 100 instructions, so Boot is a 100 MHz processor with a 1 MHz timer. When the kernel has nothing to do, it waits for the next timer tick, and the page sleeps until then instead of running in a loop.
    6. Resume at the shell loads a snapshot of the whole machine: the registers, the RAM, the timer and the serial port, saved by the boot test in node at the moment the shell printed its prompt.
    7. The processor is held against riscv-tests, the official test suite of the RISC-V instruction set. The tests are compiled with clang from the suite’s own source and run in the page. Three tests are excluded because they test hardware Boot does not have, and the page says which hardware each one needs.
    8. The inspector runs a small C program or the kernel one instruction at a time. It shows the registers and the control registers, disassembles the next instructions the way llvm-objdump does, and counts every instruction by kind.